Architectures for Computer Vision: From Algorithm to Chip by Hong Jeong

By Hong Jeong

Hong Jeong joined the dep. of electric Engineering at POSTECH in January 1988, after graduating from the dept of EECS at MIT. He has labored at Bell Labs, Murray Hill, New Jersey and has visited the dept of electric Engineering at USC. He has taught built-in classes, similar to multimedia algorithms, Verilog HDL layout, and popularity engineering, within the division of electric Engineering at POSTECH. he's drawn to illing within the gaps among machine imaginative and prescient algorithms and VLSI architectures, utilizing GPU and complex HDL languages.

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The common code template for Moore/Mealy-type finite state machines, available in mode Verilog platforms, may be useful. Verilog consists of synthesizable and unsynthesizable Verilog code. For synthesis, the following must be considered. System functions and tasks are not for synthesis but for simulation and debugging. Verilog directives are not for synthesis. The initial block is not for synthesis. The values x and z are difficult Architectures for Computer Vision 30 to use in synthesis and should typically be avoided, unless there is a very specific reason to use them.

There are a set of random number generators: $random, $dist_uniform, $dist_normal, $dist_exponential, $dist_poisson, $dist_chi_square, $dist_t, and $dist_erlang. There are integer and real math functions in Verilog system functions, which are identical to those in C. In addition to the Verilog system tasks/functions, there is a program interface with foreign functions written in C. With this interface, called VPI, the Verilog program can call user-defined functions and tasks and obtain the results.

Reg a[7:0]; //8 1-bit scalar register reg [7:0] b; //1 8-bit vector register reg c[7:0][0:255]; //8 x 256 array of 1-bit reg [0:7] d [0:255]; //256 8-bit vector indexed from 0 to 7 //The followings are allowed only in SystemVerilog. reg [1:3][7:0] e; //24-bit 3-field vector reg [1:3][7:0] f[0:255] //256 24-bit 3-field vectors reg [1:3][7:0] g[1:2][0:255] //512 24-bit 8-field vectors In the example, reg could have been replaced with any of the net or variable types. Parameters do not belong to either a net or variable type but are constants.

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